AMD EPYC™ Server Platforms

The dawn of a new era

AMD EPYC 9004 CPUs mark a new chapter in the EPYC story, with a new SP5 socket enabling support for a host of platform improvements. Leadership memory bandwidth and capacity is provided by support for 12-channels of 12TB of DDR5 memory. In addition the I/O has been upgraded to 128 lanes of PCIe 5.0, providing double the bandwidth of PCIe 4.0. Finally, switching to a new 5nm manufacturing process enables the core count to be increased from 64 to an unparalleled 128 cores. All this at the same time as providing excellent Infinity Guard cybersecurity features built into the hardware.

Expanded instruction set

The instruction set of AMD EPYC 9004 CPUs has been expanded, adding in native support for AVX-512, VNNI (Vector Neural Network Instructions) and BFLOAT16 (Brain Floating Point 16-bit) to accelerate the most demanding HPC, deep learning and AI workloads.

Leadership performance

1. Top of stack compare between AMD 96c EPYC 9654 and 64c 7763 CPUs SPECrate©2017_fp_base scores.

2. Top of stack compare between AMD 96c EPYC 9654 and Intel 40c Platinum 8380 SPECrate2017_int_base scores.

Expandable memory

In addition to the 12TB of DDR5 DRAM AMD EPYC 9004 CPUs also support Type 3 Memory Expansion modules using the CXL 1.1 protocol. CXL (Compute Express Link) is an open standard for CPU to CPU and CPU to memory connections using the same physical slots as the PCIe. The AMD EPYC 9004 platform supports CXL-compatible memory modules in two modes, memory expansion to boost bandwidth and capacity or memory pooling.

AMD Zen 4c Cores

The AMD EPYC 9704 CPUs are based on new Zen 4c architecture. These have the same overall capabilities as standard Zen 4 cores used in other EPYC 9004 CPUs but have a higher-density design, providing up to 128 cores per socket, versus the standard 96. This makes EPYC 9704 CPUs ideally suited for cloud native applications where power-efficiency and compute-density are key.

AMD 3D V-Cache

Special edition AMD EPYC 9004X CPUs feature an additional 768MB of 3D V-Cache to accelerate technical computing workflows such as structural analysis and computational fluid dynamics by up to 96%. 3D V-Cache is a separate die vertically stacked on top of the CPU die above where the existing Level 3 cache is located and connected via a bi-directional ringbus.